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VerIC
is a software company making EDA tools for the semiconductor
industry.
We specialize in the layout verification stage where extraction and netlist comparison or LVS
(Layout-vs-Schematic) are our main thrusts.
For netlist comparison we have a new, Patent Pending, approach to the problem that can
greatly improve the comparison speed and overall efficiency of the
verification process.
A layout extraction tool is also available. It can extract devices and interconnections hierarchically with a simple customer interface. |
NEWS: Free Download available.
We have free versions of our software available for download, please check them out!
NEWS: A novel parasitic extraction tool in the works.
We are working on a novel parasitic extraction tool that promises to be fast and more accurate than traditional approaches. Please stay tuned for updates on this exciting development.
NEWS: Multiple core versions to be released early summer 2008.
We are currently working on rewriting our tools for use with multiple core CPU's. We expect
a full release by early summer of 2008. This is possibly one of the earliest releases of this type of
software in the EDA industry! Stay tuned.
NEWS: An intelligent, Patent Pending, Short-finder is now available.
Have you ever been struggling to find a short in a huge layout? At VerIC Systems we have a solution
that can quickly locate a short between any nodes. We will shortly post more details on this exciting tool.
If you are one of our customers the updated software has been sent to you.
NEWS: VerIC introduces new efficient multi purpose netlist comparison tool.
A brief description of the novel features of the circuit comparison algorithm can be found here.
NEWS: VerIC releases an hierarchical extraction tool.
This novel and easy to use tool is described here.
