vericnetTopological Verification for Full Custom Designsvericnet verifies that two different design representations are topologically equivalent. It is particularly helpful when (re)designing sensitive analog blocks.Benefits: Increased Productivity vericnet is based on a patented fully hierarchical top-down methodology. This enables you to find errors quickly. Higher Quality With vericnet you can even compare abstract devices such as mutual inductors and parametrized subcircuits, making it a full-fledged schematic-vs-schematic (SVS) tool. Easy to Use vericnet is exceptionally easy to use. It features an auto-generated techfile making it possible to focus on relevant errors right away. |
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Fully hierarchical evaluation version available!
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